DRAM
DRAM is widely used in digital electronics when low-cost, high-capacity memory is required. One of the largest applications for DRAM is the main memory in modern computers and graphics cards. It is also used in many portable devices and video game consoles.
Demand for DRAM keeps increasing due to the continued growth of automotive, industrial and 5G markets. Multi-chip packaging (MCP), which combines different memories into a single small package is the main trend for DRAM in mobile devices. MCP products allow the creation of richly featured devices in small form factors at a low hardware cost and operating at minimal power consumption. To meet the need for higher density and smaller form factors, DRAM manufacturing has entered the advanced 16/10nm FinFET node.
Defect density greatly increases when the DRAM manufacturing process enters 25nm and more advanced nodes. As DRAM density increases, there’s a need to allocate more fuse memory for DRAM repair. Laser fuses used to be the main solution for DRAM repair. Now, laser fuses fail to scale sufficiently with more recent DRAM shrinks, and as a result, poly e-fuse or even newer OTP technology have become more common solutions.
eMemory’s OTP is compatible with existing DRAM processes and can be used for DRAM repair in both chip probing tests and final tests to achieve multi-time repairs, thus reducing the cost of laser trimming and time for repair setup and facilitating manufacturing flow. This post-packaging chip repair capability also significantly improves yield and benefits for MCP products.
eMemory’s aOTP also provides a wide range of VDD and VDDIO operations to make product design more flexible and save power as it is used for repair, trimming and identification in DRAM products. Moreover, our OTP’s high programming yield — requiring only a single-shot-programming pulse — greatly reduces the complexity of operations and testing costs.
Reliable and High-Endurance
FN tunneling is an ideal mechanism to program or erase the NVM cell with low power operation while building comparatively low stress over the memory cell. NeoEE utilize FN tunneling for both PGM/ERS operations therefore cause the least degradation to the gate oxide compared to other MTP technologies. Up to 100K times write cycles is mandatory for the SPD chip according to JEDEC standards. Therefore, NeoEE is the best choice for SPD application.
Wide availability and Field Programmability
eMemory’s NeoEE is available in standard logic process platforms with no additional masks and available on specialty processes like HV/BCD platforms. Meanwhile, field programmability further provides more flexibility for customers to configure their chips in different production stage and even for end-users to rewrite the settings after shipping.
Customizable for Design Flexibility
eMemory’s NeoEE IP can be customized to fulfill different design requirements. E.g., single or dual power supply, wide-range power supply, metal routing customization, substrate isolation...etc. Optional features like byte/word/page program and erase, ECC blocks, customized I/O bandwidths, and even resizable memory units can be discussed. Our wide-available “eNVM gadgets" provides obvious value for customers with great design and manufacturing flexibility.